This invention relates generally to forming semiconductor integrated circuits.
Semiconductor integrated circuits may include metal oxide semiconductor field effect transistors (MOSFETs) having a gate, source and drain. The fundamental driver of the electronics industry is transistor scaling. For the last 30 years, this has followed the trend of scaling transistor dimensions by 0.7× per process generation. This also requires that the shallow source/drain extensions be scaled by this geometric factor in order to not degrade the transistor performance.
Ideally, the shape and resistivity of the source drain extension needs to be preserved. Resistivity is maintained on a shallower junction by increasing dopant dose and activation. Increased dopant activation is achieved with advanced annealing technologies that anneal at higher temperatures in a shorter period of time. These annealing techniques are optimized to yield the correct amount of dopant diffusion and activation. As the junctions are scaled, the trend is towards lower thermal budgets for the anneal.
Traditionally, the junction depth has been scaled by reducing the diffusion time rather than the implant energy. The implant energy has been harder to scale because of an incomparability with the clean process used in semiconductor manufacturing. Dopants near the surface are removed during the clean process. In addition, there are implant tails and straggle that can impact the final shape of the source drain extension. Eventually, this will lead to a distortion of the shape of the source and drain extension shape.
Another component of the junction scaling is implant damage. The anneal step typically removes the defects. As the total amount of thermal energy is reduced to scale the junction, the residual damage can increase. This can have negative impact on the dopant activation. Novel transistor designs on fully depleted silicon over insulator (FDSOI) will have problems with recrystalization on oxide if the thin layer of silicon is amorphized. As gate oxides are scaled, the thinner film may be degraded more adversely by implant straggle and angular divergence.
One approach to reducing this damage involves applying doped glass followed by a diffusion drive-into form the junctions. The advantage of the doped glass method is that lattice damage is minimized and there is no implang damage. The limitation of this technique is that the peak concentration of dopants at the interface is lower than desirable for the modern complementary metal oxide semiconductor (CMOS) process.
Plasma doping enables doping at energies significantly lower than those of conventional implants and semiconductor processes. The substrate to be doped is placed directly in the plasma source while applying a bias to the substrate. Generally plasma doping is done at energy ranges of 200 ev to 5 keV. Ultra low energy plasma doping below 200 ev down to 10 eV have been attempted but have not been effectively integrated into transistor processes because of the incomparability with the clean process.
Thus, there is a need for better ways to form shallow junctions transistors.